{"product_id":"circuit-technology-co-optimization-of-sram-design-in-advanced-cmos-nodes-9783031761089","title":"Circuit-Technology Co-Optimization of Sram Design in Advanced CMOS Nodes","description":"\u003cp\u003e • Author(s): Hsiao-Hsuan Liu\u003cbr\u003e • Publisher: Springer\u003cbr\u003e • Publisher Imprint: Springer\u003cbr\u003e • BISAC: Embedded Computer Systems\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003cb\u003eFrom the Back Cover\u003c\/b\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp\u003eModern computing engines--CPUs, GPUs, and NPUs--require extensive SRAM for cache designs, driven by the increasing demand for higher density, performance, and energy efficiency. This book delves into two primary areas within ultra-scaled technology nodes: (1) advancing SRAM bitcell scaling and (2) exploring innovative subarray designs to enhance power-performance-area (PPA) metrics across technology nodes.\u003c\/p\u003e \u003cp\u003eThe first part of the book utilizes a bottom-up design-technology co-optimization (DTCO) approach, employing a dedicated PPA simulation framework to evaluate and identify the most promising strategies for SRAM bitcell scaling. It offers a comprehensive examination of SRAM bitcell scaling beyond 1 nm node, outlining a structured research cycle that includes identifying scaling bottlenecks, developing cutting-edge architectures with complementary field-effect transistor (CFET) technology, and addressing challenges such as process integration and routing complexities. Additionally, this book introduces a novel write margin methodology to better address the risks of write failures in resistance-dominated nodes. This methodology accounts for time-dependent parasitic bitline effects and incorporates timing setup of write-assist techniques to prevent underestimating the yield loss.\u003c\/p\u003e \u003cp\u003eIn the second part, the focus shifts to a top-down DTCO approach due to the diminishing returns of bitcell scaling beyond 5 Å node at the macro level. As technology scales, increasing resistance and capacitance (RC) lead designers to adopt smaller subarray sizes to reduce effective RC and enhance subarray-level PPA. However, this approach can result in increased inter-subarray interconnect overhead, potentially offsetting macro-level improvements. This book examines the effects of various subarray sizes on macro-level PPA and finds that larger subarrays can significantly reduce interconnect overhead and improve the energy-delay-area product (EDAP) of SRAM macro. The introduction of the active interconnect (AIC) concept enables the use of larger subarray sizes, while integrating carbon nanotube FET as back-end-of-line compatible devices results in macro-level EDAP improvements of up to 65% when transitioning from standard subarrays to AIC divided subarrays. These findings highlight the future trajectory of SRAM subarray design in deeply scaled nodes.\u003c\/p\u003e \u003cul\u003e \u003cli\u003eIdentifies and develops PPA booster within SRAM design for deeply scaled nodes.\u003c\/li\u003e \u003cli\u003eLeverages bitcell scaling to drive PPA improvements alongside technology advancements.\u003c\/li\u003e \u003cli\u003eExplores alternative subarray design to enhance PPA in interconnect-centric technology nodes.\u003c\/li\u003e \u003c\/ul\u003e","brand":"Springer","offers":[{"title":"Hardcover","offer_id":45274728693911,"sku":"9783031761089","price":8079.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0666\/3471\/1191\/files\/9783031761089.webp?v=1769280784","url":"https:\/\/atlanticbooks.com\/products\/circuit-technology-co-optimization-of-sram-design-in-advanced-cmos-nodes-9783031761089","provider":"Atlantic Books","version":"1.0","type":"link"}