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Cost-effective Methods for High-speed Nanometer CMOS VLSI Design

by Charbel Akl
Save 12% Save 12%
Current price ₹6,649.00
Original price ₹7,583.00
Original price ₹7,583.00
Original price ₹7,583.00
(-12%)
₹6,649.00
Current price ₹6,649.00

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Book cover type: Paperback
  • ISBN13: 9786208480622
  • Binding: Paperback
  • Subject: N/A
  • Publisher: LAP Lambert Academic Publishing
  • Publisher Imprint: LAP Lambert Academic Publishing
  • Publication Date:
  • Pages: 132
  • Original Price: GBP 59.94
  • Language: English
  • Edition: N/A
  • Item Weight: 186 grams
  • BISAC Subject(s): General

The semiconductor industry has been following Moore's law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.

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