{"product_id":"design-for-high-performance-low-power-and-reliable-3d-integrated-circuits-9781441995414","title":"Design for High Performance, Low Power, and Reliable 3D Integrated Circuits","description":"\u003cp\u003e • Author(s): Sung Kyu Lim\u003cbr\u003e • Publisher: Springer\u003cbr\u003e • Publisher Imprint: Springer\u003cbr\u003e • BISAC: Electronics - Circuits - General\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003cb\u003eFrom the Back Cover\u003c\/b\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp\u003eThis book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits. It includes details of numerous \"manufacturing-ready\" GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs. Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process.\u003c\/p\u003e\u003cul\u003e\n\u003cli\u003eDescribes design issues and solutions for high performance and low power 3D ICs, such as the pros\/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability.\u003c\/li\u003e\n\u003cli\u003eDiscusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the electro-migration failure mechanisms in TSVs.\u003c\/li\u003e\n\u003cli\u003eCovers design-for-thermal-reliability in 3D ICs, including thermal-aware architectural floorplanning, gate-level placement techniques to alleviate thermal problems, and co-design and co-analysis of thermal, power delivery, and performance.\u003c\/li\u003e\n\u003cli\u003eIncludes issues affecting design-for-mechanical-reliability in 3D ICs, such as the co-efficient of thermal expansion (CTE) mismatch between TSV and silicon substrate, device mobility and full-chip timing variations, and the impact of package elements.\u003c\/li\u003e\n\u003c\/ul\u003e","brand":"Springer","offers":[{"title":"Hardcover","offer_id":45275684208791,"sku":"9781441995414","price":10900.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0666\/3471\/1191\/files\/9781441995414.webp?v=1769283631","url":"https:\/\/atlanticbooks.com\/products\/design-for-high-performance-low-power-and-reliable-3d-integrated-circuits-9781441995414","provider":"Atlantic Books","version":"1.0","type":"link"}