{"product_id":"design-of-cost-efficient-interconnect-processing-units-spidergon-stnoc-9781420044713","title":"Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc","description":"\u003cp\u003e • Author(s): Marcello Coppola | Miltos D. Grammatikakis | Riccardo Locatelli\u003cbr\u003e • Publisher: CRC Press\u003cbr\u003e • Publisher Imprint: CRC Press\u003cbr\u003e • BISAC: Microprocessors\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eStreamlined Design Solutions Specifically for NoC\u003c\/strong\u003e\u003cbr\u003eTo solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eA Balanced Analysis of NoC Architecture\u003c\/strong\u003e\u003cbr\u003eAs the first detailed description of the commercial Spidergon STNoC architecture, \u003cstrong\u003eDesign of Cost-Efficient Interconnect Processing Units: Spidergon STNoC\u003c\/strong\u003e examines the highly regarded, cost-cutting technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. Employing a balanced, well-organized structure, simple teaching methods, numerous illustrations, and easy-to-understand examples, the authors explain: \u003c\/p\u003e\u003cul\u003e \u003cp\u003e \u003c\/p\u003e \u003cli\u003ehow the SoC and NoC technology works\u003c\/li\u003e \u003cli\u003ewhy developers designed it the way they did\u003c\/li\u003e \u003cli\u003ethe system-level design methodology and tools used to configure the Spidergon STNoC architecture\u003c\/li\u003e \u003cli\u003edifferences in cost structure between NoCs and system-level networks\u003c\/li\u003e \u003c\/ul\u003e\u003cp\u003eFrom professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors - all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns. \u003c\/p\u003e","brand":"CRC Press","offers":[{"title":"Hardcover","offer_id":46931680854167,"sku":"9781420044713","price":11193.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0666\/3471\/1191\/files\/9781420044713.webp?v=1771615374","url":"https:\/\/atlanticbooks.com\/products\/design-of-cost-efficient-interconnect-processing-units-spidergon-stnoc-9781420044713","provider":"Atlantic Books","version":"1.0","type":"link"}