{"product_id":"direct-transistor-level-layout-for-digital-blocks-9781402076657","title":"Direct Transistor-Level Layout for Digital Blocks","description":"\u003cp\u003e • Author(s): Prakash Gopalakrishnan\u003cbr\u003e • Publisher: Springer\u003cbr\u003e • Publisher Imprint: Springer\u003cbr\u003e • BISAC: Electronics - Circuits - General\u003c\/p\u003e\u003cp\u003eCell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing\/power are poorly handled in a fixed cell library. \u003cbr\u003e\u003cstrong\u003eDirect Transistor-Level Layout For Digital Blocks\u003c\/strong\u003e proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. \u003cbr\u003eThe essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.\u003cbr\u003e\u003cstrong\u003eDirect Transistor-Level Layout For Digital Blocks\u003c\/strong\u003e is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.\u003c\/p\u003e","brand":"Springer","offers":[{"title":"Hardcover","offer_id":45281492730007,"sku":"9781402076657","price":7277.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0666\/3471\/1191\/files\/9781402076657.webp?v=1769299357","url":"https:\/\/atlanticbooks.com\/products\/direct-transistor-level-layout-for-digital-blocks-9781402076657","provider":"Atlantic Books","version":"1.0","type":"link"}