{"product_id":"hierarchical-modeling-for-vlsi-circuit-testing-9780792390589","title":"Hierarchical Modeling for VLSI Circuit Testing","description":"\u003cp\u003e • Author(s): Debashis Bhattacharya\u003cbr\u003e • Publisher: Springer\u003cbr\u003e • Publisher Imprint: Springer\u003cbr\u003e • BISAC: General\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003eTest generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob- lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.\u003c\/p\u003e","brand":"Springer","offers":[{"title":"Hardcover","offer_id":45282082455703,"sku":"9780792390589","price":7345.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0666\/3471\/1191\/files\/9780792390589.webp?v=1769301097","url":"https:\/\/atlanticbooks.com\/products\/hierarchical-modeling-for-vlsi-circuit-testing-9780792390589","provider":"Atlantic Books","version":"1.0","type":"link"}