{"product_id":"logic-design-and-verification-using-systemverilog-revised-9781523364022","title":"Logic Design and Verification Using SystemVerilog (Revised)","description":"\u003cp\u003e • Author(s): Donald Thomas\u003cbr\u003e • Publisher: Createspace Independent Publishing Platform\u003cbr\u003e • Publisher Imprint: Createspace Independent Publishing Platform\u003cbr\u003e • BISAC: Logic Design\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003eSystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed at: -students currently in an introductory logic design course that also teaches SystemVerilog, -designers who want to update their skills from Verilog or VHDL, and -students in VLSI design and advanced logic design courses that include verification as well as design topics. The book starts with a tutorial introduction on hardware description languages and simulation. It proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design - these mirror the topics of introductory logic design courses. The book covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces. Then it covers the more advanced topics of writing testbenches including using assertions and functional coverage. A comprehensive index provides easy access to the book's topics.The goal of the book is to introduce the broad spectrum of features in the language in a way that complements introductory and advanced logic design and verification courses, and then provides a basis for further learning.Solutions to problems at the end of chapters, and text copies of the SystemVerilog examples are available from the author as described in the Preface.\u003c\/p\u003e","brand":"Createspace Independent Publishing Platform","offers":[{"title":"Paperback","offer_id":45494604955799,"sku":"9781523364022","price":6026.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0666\/3471\/1191\/files\/9781523364022.webp?v=1767151168","url":"https:\/\/atlanticbooks.com\/products\/logic-design-and-verification-using-systemverilog-revised-9781523364022","provider":"Atlantic Books","version":"1.0","type":"link"}