{"product_id":"loop-tiling-for-parallelism-9781461369486","title":"Loop Tiling for Parallelism","description":"\u003cp\u003e • Author(s): Jingling Xue\u003cbr\u003e • Publisher: Springer\u003cbr\u003e • Publisher Imprint: Springer\u003cbr\u003e • BISAC: Computer Architecture\u003c\/p\u003e\u003cp\u003eLoop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in \u003cem\u003eLoop Tiling for Parallelism\u003c\/em\u003e can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines. \u003cbr\u003e Features and key topics: \u003c\/p\u003e\u003cul\u003e \u003cli\u003e Detailed review of the mathematical foundations, including convex polyhedra and cones; \u003c\/li\u003e \u003cli\u003e Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability; \u003c\/li\u003e \u003cli\u003e Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation; \u003c\/li\u003e \u003cli\u003e A complete suite of techniques for generating SPMD code for a tiled loop nest; \u003c\/li\u003e \u003cli\u003e Up-to-date results on tile size and shape selection for reducing communication and improving parallelism; \u003c\/li\u003e \u003cli\u003e End-of-chapter references for further reading. \u003c\/li\u003e \u003c\/ul\u003e Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources.","brand":"Springer","offers":[{"title":"Paperback","offer_id":45282098872471,"sku":"9781461369486","price":10915.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0666\/3471\/1191\/files\/9781461369486.webp?v=1769301138","url":"https:\/\/atlanticbooks.com\/products\/loop-tiling-for-parallelism-9781461369486","provider":"Atlantic Books","version":"1.0","type":"link"}