{"product_id":"testing-of-interposer-based-2-5d-integrated-circuits-9783319547138","title":"Testing of Interposer-Based 2.5d Integrated Circuits","description":"\u003cp\u003e • Author(s): Ran Wang\u003cbr\u003e • Publisher: Springer\u003cbr\u003e • Publisher Imprint: Springer\u003cbr\u003e • BISAC: Electronics - Circuits - General\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003cb\u003eFrom the Back Cover\u003c\/b\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp\u003eThis book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable.\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cul\u003e\n\u003cli\u003eProvides a single-source guide to the practical challenges in testing of 2.5D ICs;\u003cbr\u003e\n\u003c\/li\u003e\n\u003cli\u003ePresents an efficient method to locate defects in a passive interposer before stacking;\u003cbr\u003e\n\u003c\/li\u003e\n\u003cli\u003eDescribes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults;\u003cbr\u003e\n\u003c\/li\u003e\n\u003cli\u003eProvides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard;\u003cbr\u003e\n\u003c\/li\u003e\n\u003cli\u003eDiscusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die;\u003cbr\u003e\n\u003c\/li\u003e\n\u003cli\u003eIncludes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.\u003cbr\u003e\n\u003c\/li\u003e\n\u003c\/ul\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e \u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e","brand":"Springer","offers":[{"title":"Hardcover","offer_id":45276551708823,"sku":"9783319547138","price":7267.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0666\/3471\/1191\/files\/9783319547138.webp?v=1769286040","url":"https:\/\/atlanticbooks.com\/products\/testing-of-interposer-based-2-5d-integrated-circuits-9783319547138","provider":"Atlantic Books","version":"1.0","type":"link"}