Progetti VLSI tolleranti alle variazioni di processo
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I gate dinamici rappresentano una scelta eccellente nella progettazione di moduli ad alte prestazioni nei moderni microprocessori. L'unico limite dei gate dinamici � il loro margine di rumore relativamente basso rispetto a quello dei gate CMOS standard. Tradizionalmente, questo problema � stato risolto utilizzando un circuito di mantenimento pMOS che compensa la corrente di dispersione della rete nMOS pull-down. Nei nodi tecnologici precedenti, il circuito di mantenimento poteva migliorare l'affidabilit� delle porte dinamiche con una penalizzazione minima in termini di prestazioni. Tuttavia, le tendenze di ridimensionamento aggressivo della tecnologia CMOS, insieme ai crescenti livelli di variazioni di processo, hanno ridotto l'efficacia dell'approccio tradizionale basato sul circuito di mantenimento. Questo problema � pi� grave nei gate dinamici a fan-in ampio a causa del gran numero di dispositivi nMOS con dispersione collegati al nodo dinamico. In questo lavoro viene proposto un gate OR dinamico a fan-in ampio tollerante alle variazioni di processo con due nuovi design di keeper, in grado di ridurre la contesa tra il keeper e il PDN e quindi di ridurre la dissipazione di potenza e il ritardo.
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