Skip to content

Booksellers & Trade Customers: Sign up for online bulk buying at trade.atlanticbooks.com for wholesale discounts

Booksellers: Create Account on our B2B Portal for wholesale discounts

Advanced ASIC Chip Synthesis: Using Synopsys(r) Design Compiler(tm) Physical Compiler(tm) and Primetime(r)

by Himanshu Bhatnagar
Save 35% Save 35%
Current price ₹16,893.00
Original price ₹25,989.00
Original price ₹25,989.00
Original price ₹25,989.00
(-35%)
₹16,893.00
Current price ₹16,893.00

Imported Edition - Ships in 12-14 Days

Free Shipping in India on orders above Rs. 500

Request Bulk Quantity Quote
+91
Book cover type: Hardcover
  • ISBN13: 9780792376446
  • Binding: Hardcover
  • Subject: N/A
  • Publisher: Springer
  • Publisher Imprint: Springer
  • Publication Date:
  • Pages: 328
  • Original Price: EUR 229.99
  • Language: English
  • Edition: 2002
  • Item Weight: 726 grams
  • BISAC Subject(s): Electrical, Logic Design, and Electronics / Circuits / General

Advanced ASIC Chip Synthesis: Using Synopsys(R) Design Compiler(R) Physical Compiler(R) and PrimeTime(R), Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.

Trusted for over 49 years

Family Owned Company

Secure Payment

All Major Credit Cards/Debit Cards/UPI & More Accepted

New & Authentic Products

India's Largest Distributor

Need Support?

Whatsapp Us