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An Introduction to RISC V. "Reduced Instruction Set Computer" Processor

by Arpita Patel
Save 12% Save 12%
Current price ₹3,312.00
Original price ₹3,783.00
Original price ₹3,783.00
Original price ₹3,783.00
(-12%)
₹3,312.00
Current price ₹3,312.00

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Book cover type: Paperback
  • ISBN13: 9783389028421
  • Binding: Paperback
  • Subject: N/A
  • Publisher: Grin Verlag
  • Publisher Imprint: Grin Verlag
  • Publication Date:
  • Pages: 38
  • Original Price: GBP 29.9
  • Language: English
  • Edition: N/A
  • Item Weight: 64 grams
  • BISAC Subject(s): Languages / General

Document from the year 2024 in the subject Computer Science, grade: A, language: English, abstract: RISC-V, an open-source Instruction Set Architecture (ISA), has become a significant performer in the realm of computer architecture, challenging traditional proprietary designs and opening the doors for innovation and customization. Initially in this work, RISC-V's historical evolution, its architecture, including its design concepts, instruction set, register file and implementations, were understood through a literature survey.A comprehensive literature survey is conducted on various variants of RISC-V family and their applications, which include lowering total costs, speeding up processor execution, consuming less power, and creating a more manageable and compact versions of the original architecture. The study includes a thorough analysis of several RISC-V variations. According to review of the literature, the 32-bit biRISC-V processor core is the newest member of the RISC-V family and using superscalar dual issue design to increase processor overall throughput.

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