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Compilation Techniques for Reconfigurable Architectures

by João M. P. Cardoso
Save 35% Save 35%
Current price ₹7,277.00
Original price ₹11,194.00
Original price ₹11,194.00
Original price ₹11,194.00
(-35%)
₹7,277.00
Current price ₹7,277.00

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Book cover type: Paperback
  • ISBN13: 9781441935106
  • Binding: Paperback
  • Subject: N/A
  • Publisher: Springer
  • Publisher Imprint: Springer
  • Publication Date:
  • Pages: 223
  • Original Price: EUR 99.99
  • Language: English
  • Edition: N/A
  • Item Weight: 362 grams
  • BISAC Subject(s): Oncology / General, Computer Architecture, and Electrical

From the Back Cover

This book describes a wide range of code transformations and mapping techniques for compiling programs written in high-level programming languages to reconfigurable architectures. While many of these transformations and mapping techniques have been developed in the context of compilation for traditional architectures and high-level synthesis, their application to reconfigurable architectures poses a whole new set of challenges- particularly when targeting fine-grained reconfigurable architectures such as contemporary Field-Programmable Gate-Arrays (FPGAs).

Organized in eight chapters, this book provides a helpful structure for practitioners and graduate students in the area of computer science and electrical and computer engineering to effectively map computations to reconfigurable architectures.

Key Features:

  • Introduces the reader to hardware compilation and reconfigurable computing architectures.
  • Presents a range of compiler code transformations and mapping techniques focusing on imperative programming languages.
  • Allows the reader to bridge the gap between the software compilation and the hardware compilation and synthesis domains.
  • Brings a number of compilation techniques together into one structured source, and includes representative examples of their applications.

  • Provides a historical perspective on representative compilation research efforts over the last 15 years.
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