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Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS

by Brandon Noia
Save 35% Save 35%
Current price ₹7,470.00
Original price ₹11,492.00
Original price ₹11,492.00
Original price ₹11,492.00
(-35%)
₹7,470.00
Current price ₹7,470.00

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Book cover type: Paperback
  • ISBN13: 9783319345345
  • Binding: Paperback
  • Subject: N/A
  • Publisher: Springer
  • Publisher Imprint: Springer
  • Publication Date:
  • Pages: 245
  • Original Price: EUR 102.79
  • Language: English
  • Edition: Softcover Repri
  • Item Weight: 451 grams
  • BISAC Subject(s): Computer Architecture, Electronics / Semiconductors, and Hardware / Mainframes & Minicomputers

From the Back Cover

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

- Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs;
- Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations;
- Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.

Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.

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