Digitale Schaltkreise mit Techniken zur Reduzierung der Verlustleistung unterhalb der Schwelle
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Die zahlreichen Forschungsbem�hungen im Bereich des VLSI-Designs mit geringer Leistung nahmen mit der steigenden Nachfrage nach tragbaren elektronischen Ger�ten zu. Aufgrund der fortschrittlichen IC-Technologie nimmt die minimale Strukturgr� e von VLSI-Schaltungen weiter ab. Die Hersteller von VLSI-Chips nutzen den Vorteil der m�glichen Reduzierung der Strukturgr� e effektiv aus, indem sie die bestehenden Designs von VLSI-Chips skalieren (verkleinern), wodurch die Geschwindigkeit der Schaltung erh�ht werden kann. Die Verkleinerung der Geometrie von Transistoren und die exponentiell wachsende Anzahl von Transistoren auf einem einzelnen Chip haben dazu gef�hrt, dass das Energiemanagement f�r VLSI-Designs von entscheidender Bedeutung ist. Der Verlust durch Leckstr�me unterhalb des Schwellenwerts ist der Hauptbestandteil der Verlustleistung in VLSI-Schaltungen. Dieser Verlust muss reduziert werden, damit die Energie besser genutzt werden kann. Techniken wie CMOS, Stack, Sleep und Sleepy Keeper werden zur Kontrolle von Verlusten durch Leckstr�me unterhalb des Schwellenwerts eingesetzt. Diese effektiven Techniken zur Entwicklung von digitalen Schaltkreisen mit geringer Leistung reduzieren die Gesamtverlustleistung. Die Eigenschaften von digitalen Schaltkreisen wie Inverter, NAND, NOR, EXKLUSIV-ODER, HALB-ADDIERER und HALB-SUBTRAHIERER werden analysiert und in verschiedenen Technologien wie 45 nm, 120 nm und 180 nm verglichen.
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