Electrostatic discharge (ESD) continues to impact semiconductor components and systems as technologies scale from micro- to nano-electronics.
This book studies electrical overstress, ESD, and latchup from a whole-chip ESD design synthesis approach. It provides a clear insight into the integration of ESD protection networks from a generalist perspective, followed by examples in specific technologies, circuits, and chips. Uniquely both the semiconductor chip integration issues and floorplanning of ESD networks are covered from a ‘top-down' design approach.
Look inside for extensive coverage on:
*integration of cores, power bussing, and signal pins in DRAM, SRAM, CMOS image processing chips, microprocessors, analog products, RF components and how the integration influences ESD design and integration *architecturing of mixed voltage, mixed signal, to RF design for ESD analysis *floorplanning for peripheral and core I/O designs, and the implications on ESD and latchup *guard ring integration for both a ‘bottom-up' and ‘top-down' methodology addressing I/O guard rings, ESD guard rings, I/O to I/O, and I/O to core *classification of ESD power clamps and ESD signal pin circuitry, and how to make the correct choice for a given semiconductor chip *examples of ESD design for the state-of-the-art technologies discussed, including CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, and smart power *practical methods for the understanding of ESD circuit power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics
ESD: Design and Synthesis is a continuation of the author's series of books on ESD protection. It is an essential reference for: ESD, circuit, and semiconductor engineers; design synthesis team leaders; layout design, characterisation, floorplanning, test and reliability engineers; technicians; and groundrule and test site developers in the manufacturing and design of semiconductor chips.
It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, and manufacturing sciences, and on courses involving the design of ESD devices, chips and systems. This book offers a useful insight into the issues that confront modern technology as we enter the nano-electronic era.
Dr. Steven H. Voldman, IEEE Fellow, Vermont, USA
Prolific Wiley writer, Dr. Steven Voldman has been involved with ESD work since 1991. He has been Chairman of the ESD Association WG 5.5 on TLP testing since 2001 and he was Chairman of the SEMATECH ESD Working Group on ESD Technology from 1995 until 1998.
Dr. Voldman worked 25 years at IBM before working at Qimonda in 2007 and then TSMC Corporation in 2008. Currently he holds 181 patents in the areas of ESD and latchup, and has 125 pending. His fields of expertise are electrostatic discharge (ESD) protection, latchup, ESD testing and ESD design. To date he has worked on many design architectures from SRAM, DRAM, ASICs, Microprocessors, NVRAMs, image processing designs and power technology.
