Getting RTL to compile is easy. Getting a design through verification, synthesis, timing closure, physical implementation and signoff is where electronic design becomes engineering.
Foundations of Electronic Design Automation: From Physics to Implementation - Volume 2 moves directly into that territory.
This volume begins with the languages, models and verification systems used to express complex hardware-and follows those representations all the way through synthesis, timing analysis, physical design and the modern automated EDA workflow.
The objective is not to teach isolated commands.
It is to show how an electronic design becomes trustworthy silicon.
You will work through VHDL and the IEEE 1076 model of strongly typed concurrent hardware description, then move into GHDL and open-source simulation and synthesis workflows. Property Specification Language introduces temporal properties and assertion-based verification. SystemC extends the design space into transaction-level modelling, executable architecture and high-level synthesis.
From there, the book moves deeper into the machinery of EDA itself.
C++ is examined as a language for hardware models, simulation infrastructure and high-performance design tools. Chisel, FIRRTL and Clash demonstrate how modern programming-language concepts can generate and transform hardware while maintaining structural and type-level guarantees.
Then the focus shifts from describing hardware to turning it into an implementation that can actually close.
Volume 2 covers:
- VHDL design, synthesis and testbench methodology
- GHDL simulation and GHDL-Yosys workflows
- PSL temporal logic and formal properties
- SystemC and transaction-level modelling
- Modern C++ for EDA engineering
- Verilator and HDL/software integration
- Chisel, FIRRTL and hardware generation
- Clash and type-driven hardware design
- Boolean optimisation and logic synthesis
- Technology mapping and FPGA synthesis
- Static timing analysis
- Setup, hold, delay modelling and timing constraints
- Multi-mode multi-corner timing closure
- Functional, assertion-based and formal verification
- Hardware/software co-verification
- Floorplanning and placement
- Clock-tree synthesis and routing
Every EDA stage is a transformation-and every transformation can lose information, introduce assumptions or hide a failure.
A clean simulation does not prove synthesizability.
A synthesized netlist does not prove timing closure.
Timing closure does not prove manufacturability.
And an AI-generated design that looks convincing does not prove anything until it has passed the same verification discipline demanded of human-written hardware.
Volume 2 therefore concentrates on the evidence required at each stage: assertions, coverage, equivalence, constraints, timing reports, extracted parasitics, design-rule checks, reproducible automation and final signoff.
You will learn not merely how to operate an EDA flow, but how to interrogate it.
What changed? What assumption was introduced? What constraint governs the result? What evidence proves that the implementation still satisfies the original intent?
Those questions separate tool users from engineers capable of diagnosing failures across an entire chip-design flow.
For readers working in digital design, FPGA development, ASIC engineering, verification, physical design, EDA software or AI-assisted semiconductor design, Volume 2 takes the journey from hardware representation to implementation, verification and signoff.
Because ultimately, silicon does not care whether the RTL looked elegant.
It either works-or it does not.
