From the Back Cover
A subtle change that leads to disastrous consequences--hardware Trojans undoubtedly pose one of the greatest security threats to the modern age. How to protect hardware against these malicious modifications? One potential solution hides within logic locking; a prominent hardware obfuscation technique. In this book, we take a step-by-step approach to understanding logic locking, from its fundamental mechanics, over the implementation in software, down to an in-depth analysis of security properties in the age of machine learning. This book can be used as a reference for beginners and experts alike who wish to dive into the world of logic locking, thereby having a holistic view of the entire infrastructure required to design, evaluate, and deploy modern locking policies.
- Provides a comprehensive introduction to logic locking, suitable for beginners and experts;
- Offers a novel perspective on hardware Trojan classification and its interplay with logic locking;
- Presents details on the design and implementation of a silicon-ready logic-locking software framework;
- Introduces scaling techniques to design and apply logic locking to complex hardware components, such as processors;
- Presents novel ways of evaluating the security of logic locking with machine learning.
Dominik Sisejkovic received the B.Sc. and M.Sc. degree in software engineering from the Faculty of Electrical Engineering and Computing, University of Zagreb, Croatia, in 2014 and 2016, respectively. In February 2022, he received the Ph.D. (Dr.-Ing.) degree with the highest honors from the Faculty of Electrical Engineering and Information Technology, RWTH Aachen University, Germany. From 2016 to 2022, he worked as a research assistant at the Chair for Software for Systems on Silicon (SSS) at the RWTH Aachen University. In his doctoral work, he contributed to various aspects of logic locking (a hardware protection methodology), focusing on software tools to prevent malicious design modifications (hardware Trojans) within hardware designs. In addition, he was directly involved in the design and implementation of the logic-locking software framework that was applied for the production of the first logic-locked RISC-V processor core on the market. For his contributions, he received the best Ph.D. award at the IFIP/IEEE VLSI-SoC conference (2021), the ICT young researcher award by RWTH Aachen University for significant contributions in the ICT research area (2020), and the HiPEAC technology transfer award for successfully transferring a scalable logic-locking framework for hardware integrity protection to the industry (2020). Furthermore, since 2019, he has co-organized the annual SeHAS workshop on Secure Hardware, Architectures and Operating Systems at the HiPEAC conference. Since 2020, he has been part of the technical committee for the hardware and systems security track at the International Symposium on Quality Electronic Design (ISQED).Rainer Leupers received the M.Sc. (Dipl.-Inform.) and Ph.D. (Dr. rer. nat.) degrees in Computer Science with honors from TU Dortmund in 1992 and 1997. From 1997-2001 he was the Chief Engineer at the Embedded Systems Chair at TU Dortmund. In 2002, he joined RWTH Aachen University as a professor for Software for Systemson Silicon. His research comprises embedded software development tools, system-on-chip architectures, hardware security, and electronic design automation. He served in committees of the leading international EDA conferences and received various scientific awards, including Best Paper Awards at DAC and twice at DATE, as well as several industrial awards. Dr. Leupers is also engaged as an entrepreneur and in turning research results into innovations. He holds several patents and has been a co-founder of LISATek (now with Synopsys), Silexica (acquired by Xilinx), and Secure Elements. As the coordinator of the TETRACOM and TETRAMAX projects, he created a structured approach to academia-to-industry technology transfer with 100+ successful instances across Europe.
