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Low Power Networks-On-Chip

by Cristina Silvano
Save 35% Save 35%
Current price ₹10,283.00
Original price ₹15,819.00
Original price ₹15,819.00
Original price ₹15,819.00
(-35%)
₹10,283.00
Current price ₹10,283.00

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Book cover type: Hardcover
  • ISBN13: 9781441969101
  • Binding: Hardcover
  • Subject: N/A
  • Publisher: Springer
  • Publisher Imprint: Springer
  • Publication Date:
  • Pages: 287
  • Original Price: EUR 139.99
  • Language: English
  • Edition: N/A
  • Item Weight: 608 grams
  • BISAC Subject(s): Electronics / Circuits / VLSI & ULSI and Design, Graphics & Media / CAD-CAM

From the Back Cover
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. -Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; -Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; -Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.

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