Skip to content

Booksellers & Trade Customers: Sign up for online bulk buying at trade.atlanticbooks.com for wholesale discounts

Booksellers: Create Account on our B2B Portal for wholesale discounts

Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors

by Jean-Loup Baer
Save 2% Save 2%
Current price ₹10,107.00
Original price ₹10,270.00
Original price ₹10,270.00
Original price ₹10,270.00
(-2%)
₹10,107.00
Current price ₹10,107.00

Imported Edition - Ships in 18-21 Days

Free Shipping in India on orders above Rs. 500

Request Bulk Quantity Quote
+91
Book cover type: Hardcover
  • ISBN13: 9780521769921
  • Binding: Hardcover
  • Subject: N/A
  • Publisher: Cambridge University Press
  • Publisher Imprint: Cambridge University Press
  • Publication Date:
  • Pages: 382
  • Original Price: GBP 79.0
  • Language: English
  • Edition: 1
  • Item Weight: 840 grams
  • BISAC Subject(s): Computer Architecture

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as - the policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers - optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations - design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors - state-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

Baer, Jean-Loup: - Jean-Loup Baer is Professor Emeritus of Computer Science and Engineering at the University of Washington, where he has been since 1969. Professor Baer is the author of Computer Systems Architecture and more than 100 refereed papers. He is a Guggenheim Fellow, an ACM Fellow, and an IEEE Fellow. Baer has held several editorial positions, including editor-in-chief of the Journal of VLSI and Computer Systems and editor of the IEEE Transactions on Computers, the IEEE Transactions on Parallel and Distributed Systems, and the Journal of Parallel and Distributed Computing. He has served as General Chair and Program Chair of several conferences, including ISCA and HPCA.

Trusted for over 49 years

Family Owned Company

Secure Payment

All Major Credit Cards/Debit Cards/UPI & More Accepted

New & Authentic Products

India's Largest Distributor

Need Support?

Whatsapp Us