From the Back Cover
The IC industry, including digital and analog circuit design houses, electrical design automation software vendors, library and IP providers, and foundries all face grand challenges in designing nanometer VLSI systems.
The design productivity gap between nanometer VLSI technologies and today's design capabilities mainly comes from the exponentially growing complexity of VLSI systems due to relentless pushing for integration. The physical effects on the performance and reliability of these systems are becoming more pronounced. Efficient modeling and reduction of both the passive and active circuits is essential for hierarchical and IP-based reuse design paradigms.
Symbolic Analysis and Reducation of VLSI Circuits presents the symbolic approach to the modeling and reduction of both the passive parasitic linear networks and active analog circuits. It reviews classic symbolic analysis methods and presents state-of-art developments for interconnect reduction and the behavioral modeling of active analog circuits. The text includes the most updated discoveries such as Y-Delta transformation and DDD-graph symbolic representation which allow analysis and modeling of much larger circuitry than ever before.
Zhanhai Qin received his B.S. degree in computer science and technology from Tsinghua University in 1999, and his Ph.D. degree in computer science and engineering from University of California, San Diego in 2003. He is now working at Synopsys Inc. His research interests include circuit analysis and simulation, signal integrity issues in deep sub-micron VLSI designs.
Sheldon X.-D. Tan received his B.S. and M.S. degrees in electrical engineering from Fudan University, Shanghai, China in 1992 and 1995, respectively and his Ph.D. in electrical and computer engineering from the University of Iowa, Iowa City, in 1999. He is an Assistant Professor in the Department of Electrical Engineering, University of California, Riverside. His research interests include several aspects of design automation for VLSI integrated circuits -- modeling, analysis and optimization of mixed-signal/RF/analog circuits, high-performance and intelligent embedded systems, signal integrity issues in VLSI physical design, high performance power/ground distribution network design and optimization. Dr. Tan received a Best Paper Award from the 1999 IEEE/ACM Design Automation Conference.
Chung-Kuan Cheng received B.S. and M.S. degrees in electrical engineering from National Taiwan University, and a Ph.D. in electrical engineering and computer sciences from University of California, Berkeley in 1984. He is a Professor in the Computer Science and Engineering Department, University of California, San Diego, and an IEEE fellow. He received the best paper award IEEE Trans. on Computer-Aided Design in 1997, and in 2002 received the NCR excellence in teaching award from the UCSD School of Engineering. His research interests include circuit analysis, physical synthesis, and interconnect optimization.
