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System-on-Chip Test Architectures: Nanometer Design for Testability

by Laung-Terng Wang
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Current price ₹4,896.00
Original price ₹8,160.00
Original price ₹8,160.00
Original price ₹8,160.00
(-40%)
₹4,896.00
Current price ₹4,896.00

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Book cover type: Hardcover
  • ISBN13: 9780123739735
  • Binding: Hardcover
  • Subject: N/A
  • Publisher: Morgan Kaufmann Publishers
  • Publisher Imprint: Morgan Kaufmann Publishers
  • Publication Date:
  • Pages: 896
  • Original Price: USD 84.95
  • Language: English
  • Edition: N/A
  • Item Weight: 1579 grams
  • BISAC Subject(s): Logic Design, Electrical, and Industrial Design / Product

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

Wang, Laung-Terng: - Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).

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